1. Technical Field
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device having a plurality of stacked semiconductor chips and a method for manufacturing a semiconductor device.
2. Background Art
In recent years, lighter, more compact and more sophisticated semiconductor devices are generally required in the industry, and a dense integration of electronic components and a dense installation of electronic components are progressed. Semiconductor packages employed for these electronic equipments are miniaturized and have multiple pins, and further, substrates for packaging electronic components including semiconductor packages are also miniaturized.
Typical semiconductor packages that achieves a high-density package include a stack structure, in which a plurality of semiconductor chips are stacked on an interconnect substrate. When a combination of a larger semiconductor chip and a smaller semiconductor chip are stacked in such structure, the larger semiconductor chip is mounted on the interconnect substrate and the smaller semiconductor chip is mounted on the larger semiconductor chip.
On the contrary, a package-on-package (POP) structure is proposed for another type of a structure including a stacked combination of a larger semiconductor chip and a smaller semiconductor chip, in which the smaller semiconductor chip is mounted on the mounting substrate (see Japanese Patent Laid-Open No. H7-183,426 (1995) and Japanese Patent Laid-Open No. H7-249,736 (1995)).
In such POP structure, a substrate including a second semiconductor chip mounted thereon is mounted on a mounting substrate including a first semiconductor chip mounted thereon. For example, when the first semiconductor chip is smaller than the second semiconductor chip, the above-described relationship in the sizes of the chips is provided.
In the POP structure, it is required that the mounting substrate is electrically connected to the first semiconductor chip and a space for mounting the second semiconductor chip is ensured in the mounting substrate.
To fulfill the requirements, Japanese Patent Laid-Open No. H7-183,426 discloses a configuration of a semiconductor device, which is provided with a bump electrode having a height, which larger than a thickness of the semiconductor chip mounted on the mounting substrate. Then, another substrate having another semiconductor chip mounted thereon is disposed on such bump electrode, and these are electrically connected to ensure an electrical conduction between the semiconductor chip on the substrate and the mounting substrate.
In addition, in a semiconductor assembly as set forth in Japanese Patent Laid-Open No. H7-249,736, “J”-shaped leads are provided in the assembly, and a bottom of a lead in the upper portion of the assembly is coupled to an upper surface of a lead in the lower portion of the assembly.
Patent literature 1
    Japanese Patent Laid-Open No. H7-183,426Patent literature 2    Japanese Patent Laid-Open No. H7-249,736
However, a stress is exerted on the bump electrode or the lead when a thermal history is encountered in the conventional POP structures described above to cause a break in the bump electrode or the lead, causing a conductive failure. It is considered this is because a larger difference exists between a coefficient of thermal expansion of the substrate and a coefficient of thermal expansion of the bump electrode for the vertical electrical conduction or between a coefficient of thermal expansion of the lead and a coefficient of thermal expansion of the substrate, and in addition, because larger bump electrode and larger lead that are thicker than the thickness of semiconductor chip are employed.